1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and, more particularly, relates to a data output circuit which operates at high speed.
2. Description of the Related Art
For the processing of moving image data, a further increase in the presently attained high data transfer rate is required. Conventionally, in order to increase the data transfer rate, a technique of using a plurality of data lines to realize simultaneous data transfer and conducting the simultaneous data transfer at a high speed has been employed. In such a technique, one driver circuit is required for every data line for the interface with the outside of the chip. Since such a driver circuit drives a load capacitance, the current consumption becomes larger as the transfer speed is increased. This causes an insufficient power supply if the driver circuit is configured to receive power from a power supply line used in common with other circuits. This causes a drop of the supply potential and the like, as well as causing unstable operations of other circuits. In order to overcome this problem, the driver circuit is conventionally provided with individual power supplies VDDQ and VSSQ.
However, at the operation of a driver, a source potential of a MOS transistor constituting the driver changes due to a parasitic capacitance between a gate and a source of the MOS transistor. This adversely affects a signal transfer rate of data.
FIG. 14A is a circuit diagram for illustrating the prior art problem. FIG. 14B is a waveform chart showing the simulation results of the operation of the circuit of FIG. 14A conducted by the inventors of the present invention.
As shown in FIG. 14A, a driver 5 corresponding to one data unit is composed of a p-type MOS transistor 101 and an n-type MOS transistor 102.
In the case where a signal input into the driver 5 transfers from a high level (HIGH) to a low level (LOW) during a time t1 as shown in FIG. 14B, a signal output from the driver 5 transfers from LOW to HIGH. At this time, source potentials int.VDDQ and int.VSSQ drop due to a gate-source parasitic capacitance 111 generated in the MOS transistor 101 and a gate-source parasitic capacitance 112 generated in the MOS transistor 102, during the time t1 as shown in FIG. 14B.
Power supplies VDDQ and VSSQ for applying a voltage to the driver 5 are provided individually from other circuits as described above. When an independent power supply is provided to each driver, the supply capacity at the driver is small, and no element other than the transistor constituting the driver 5 exists at a supply node of the driver 5. Accordingly, when a parasitic capacitance is generated between a gate and a source of the same transistor of the driver 5, the potential at a source node of the transistor of the driver 5 transfers depending on a change in the gate potential of the driver 5. As a result, the time period during which the potential at a pad P1 which is the output terminal of the driver 5 is established is delayed by a time t2 compared with an ideal case.
In particular, when the driver 5 drives a load at a high frequency, the change in the potential at the source node greatly affects the operation of the driver 5. The source node is connected to the power supply VDDQ or VSSQ via a bonding wire which has an inductance L, as shown in FIG. 14A. The inductance L prevents charges from being supplied to and drained from the source node.
FIG. 15 is a graph showing the simulation results of the change in the potential at the source node when the potential at a node A of the circuit shown in FIG. 14A transfers from HIGH to LOW, conducted by the inventors of the present invention. More specifically, FIG. 15 shows the changes (P200, P400, P600, P800, P1000) in the potentials at the source node observed when the time period during which the potentials (A200, A400, A600, A800, A1000) at the node A transfer from 1.5 volts to 0 volt is changed between 200 picoseconds (ps) and 1 nanosecond (ns).
A curve P200 shows that the change in the potential at the source node cannot be suppressed within 10% of the constant voltage (1.5 V) when a signal at the node A transfers from HIGH to LOW in 200 ps. In general, the transfer period (twice the transfer time (e.g., HIGH to LOW) described above) is 50% or less of a signal period. For example, in the case where the curve P200 represents part of a signal which transfers from HIGH to LOW in 200 ps, remains LOW for 200 ps, transfers from LOW to HIGH in 200 ps, and remains HIGH for 200 ps, the frequency of this signal is 1.25 GHz. Assuming that the gate-source voltage is 1.5 V and the threshold voltage of the transistor is 0.5 V, if the potential at the source node drops by 10%, the driving current of the transistor of the driver drops by 30%, delaying the timing at which the transistor is turned on. Specifically, a delay of several hundred picoseconds is generated until the data to be output by the driver is established. The drop of the potential at the source node becomes greater if a signal having a frequency of 1.25 GHz or more is input into the driver of FIG. 14A. This further increases the time required until the value of data to be output by the driver is established.
Thus, as is observed from FIG. 15, it is difficult to output data at a frequency of 1 GHz or more from the circuit of FIG. 14A due to the delay described above.